Word-Level Symbolic Trajectory Evaluation

نویسندگان

  • Supratik Chakraborty
  • Zurab Khasidashvili
  • Carl-Johan H. Seger
  • Rajkumar Gajavelly
  • Tanmay Haldankar
  • Dinesh Chhatani
  • Rakesh Mistry
چکیده

Symbolic trajectory evaluation (STE) is a model checking technique that has been successfully used to verify industrial designs. Existing implementations of STE, however, reason at the level of bits, allowing signals to take values in {0, 1, X}. This limits the amount of abstraction that can be achieved, and presents inherent limitations toion that can be achieved, and presents inherent limitations to scaling. The main contribution of this paper is to show how much more abstract lattices can be derived automatically from RTL descriptions,lattices can be derived automatically from RTL descriptions, and how a model checker for the general theory of STE instantiated with such abstract lattices can be implemented in practice. This gives us the first practical word-level STE engine, called STEWord. Experiments on a set of designs similar to those used in industry show that STEWord scales better than word-level BMC and also bit-level STE.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Symbolic trajectory evaluation for word-level verification: theory and implementation

Symbolic trajectory evaluation (STE) is a model checking technique that has been successfully used to verify many industrial designs. Existing implementations of STE reason at the level of bits, allowing signals in a circuit to take values from a lattice comprised of three elements: 0, 1, and X. This limits the amount of abstraction that can be achieved, and presents limitations to scaling STE ...

متن کامل

Formal Veriication by Symbolic Evaluation of Partially-ordered Trajectories

Symbolic trajectory evaluation provides a means to formally verify properties of a sequential system by a modiied form of symbolic simulation. The desired system properties are expressed in a notation combining Boolean expressions and the temporal logic \next-time" operator. In its simplest form, each property is expressed as an assertion A =) C], where the antecedent A expresses some assumed c...

متن کامل

Formal Veri cation by Symbolic Evaluation of Partially - OrderedTrajectories

Symbolic trajectory evaluation provides a means to formally verify properties of a sequential system by a modiied form of symbolic simulation. The desired system properties are expressed in a notation combining Boolean expressions and the temporal logic \next-time" operator. In its simplest form, each property is expressed as an assertion A =) C], where the antecedent A expresses some assumed c...

متن کامل

Exploiting Symmetry When Verifying Transistor-level Circuits by Symbolic Trajectory Evaluation

In this paper we describe the use of symmetry for verii-cation of transistor-level circuits by symbolic trajectory evaluation. We show that exploiting symmetry can allow one to verify systems several orders of magnitude larger than otherwise possible. We classify symmetries in circuits as structural symmetries, arising from similarities in circuit structure, data symmetries, arising from simila...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2015